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ISL22102
Dual, Audio, Push-button Controlled Potentiometer (XDCPTM)
Data Sheet January 14, 2010 FN6788.1
32 Tap, Push-button, Dual Audio Logarithmic Potentiometer with Buffer Amplifiers and Audio Detection
The ISL22102 integrates two digitally controlled potentiometers (DCP) with buffered wiper outputs and an internal bias voltage generator (VB) on a monolithic CMOS integrated circuit. The wiper position is adjusted by the user through simple Up and Down push buttons, ideal for stereo volume control in audio applications. Each potentiometer is implemented using 31 polysilicon resistors in a logarithmic array. Between each of the resistors are tap points connected to the wiper terminal through switches. When powered up, the wipers are reset to the -20dB position. In addition to the ISL22102's low noise design, the ISL22102 also contains a zero-crossing detection circuitry to further minimize click and pop noise during volume transition. The internal VB generator of the ISL22102 provides a precision middle scale voltage reference that reduces external circuitry and simplifies application design. The ISL22102 implements two power saving techniques for power critical applications. It is a Standby Mode that can be enabled to reduce the power consumption of the part when DCP is not in use. The part also has Audio Detection circuitry that provides an indication FLAG to external devices and services. The FLAG can be delayed through D0, D1 and D2 pin configuration. By connecting the FLAG to the standby pin (SB), it will automatically put the part into Standby Mode.
Features
* Dual Audio Control - Two 32 Taps Log Pots * Buffered Wiper Outputs * Audio Detection with Threshold Input and Controlled Delay * Zero Amplitude Wiper Switching (ZAWS) * Simple Push-button Interface * Auto Increment/decrement After 1s Button Press * Standby Mode * Mute Function * Total Resistance: 18.5k each DCP (Typical) * Voltage Operation - VCC = 2.7V to 5.5V - AVCC = 2.7V to 5.5V * Temp Range = -40C to +85C * Package Options - 20 Ld TSSOP - 20 Ld QFN * Pb-Free (RoHS Compliant)
Audio Performance
* 0dB to -72dB Volume Control * -90dB Mute * SNR: -90dB * THD+N: 0.01% @ 1kHz
Pinout
ISL22102 (20 LD QFN) TOP VIEW
FLAG SB UP D2 D1
* Crosstalk Rejection: -100dB @ 1kHz * Channel-to-Channel Variation: 0.1dB * Mid point 3dB-Cutoff: 100kHz
20 DN MUTE VCC AVCC LEFT_IN 1 2 3 4 5 6 LEFT_OUT
19
18
17
16 15 D0
Applications
* Set Top Boxes * Stereo Amplifiers
14 VTH 13 GND 12 HPB 11 HPA
* DVD Players * Portable Audio Products
7 CB
8 VB
9 RIGHT_OUT
10 RIGHT_IN
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2008, 2010. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ISL22102 Ordering Information
PART NUMBER (Note) ISL22102IV20Z* ISL22102IR20Z* PART MARKING 22102 IVZ 221 02IRZ TOTAL RESISTANCE (k) 18.5 18.5 TEMP RANGE (C) -40 to +85 -40 to +85 PACKAGE (Pb-Free) 20 Ld TSSOP 20 Ld QFN PKG. DWG.# M20.173 L20.4x4C
*Add "-TK" suffix for tape and reel. Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
Block Diagram
AVCC LEFT_IN 32-TAP LOG 18.5k VB + + 2.5M CB 2.5M 32-TAP LOG 18.5k RIGHT_IN RIGHT_OUT + GND HPA HPB VTH AUDIO DETECT AND DELAY VCC CONTROL UNIT FLAG LEFT_OUT
UP
DN
MUTE
SB
D0
D1
D2
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ISL22102 Pinouts
ISL22102 (20 LD QFN) TOP VIEW
FLAG UP SB D2 D1 FLAG SB UP DN MUTE VCC AVCC LEFT_IN 1 2 3 4 5 6 LEFT_OUT 7 CB 8 VB 9 RIGHT_OUT 10 RIGHT_IN 15 D0 14 VTH 13 GND 12 HPB 11 HPA DN MUTE VCC AVCC LEFT_IN LEFT_OUT 1 2 3 4 5 6 7 8 9
ISL22102 (20 LD TSSOP) TOP VIEW
20 D2 19 D1 18 D0 17 VTH 16 GND 15 HPB 14 HPA 13 RIGHT_IN 12 RIGHT_OUT 11 VB
20
19
18
17
16
CB 10
Pin Description
PIN (QFN) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 EPAD* PIN (TSSOP) 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 1 2 3 SYMBOL DN MUTE VCC AVCC LEFT_IN LEFT_OUT CB VB RIGHT_OUT RIGHT_IN HPA HPB GND VTH D0 D1 D2 FLAG SB UP FUNCTION Active low volume decrement input with internal pull-up. Active low mute input with internal pull-up. Digital Power Supply. Analog Power Supply. Input terminal of the Left Channel Potentiometer. Referenced to VB. Left channel output. Referenced to VB. Terminal for external bypass capacitor to GND. AVCC/2 reference output. Can be used as a signal reference for other system components. Right channel output. Referenced to VB. Input terminal of the Right Channel Potentiometer. Referenced to VB. Terminal A of audio-detector high pass filter capacitor. Terminal B of audio-detector high pass filter capacitor. System Ground. Overall for analog and digital power supply. Analog Input threshold for audio detection. Require an external resistor to VB. Programming bit (LSB) input for delayed FLAG low output. Programming bit input for delayed FLAG low output. Programming bit (MSB) input for delayed FLAG low output. Output signal indicates audio input detection. Active low Standby Mode input with internal pull-up. Active low volume increment input with internal pull-up. Exposed Die Pad internally connected to GND
*Note: PCB thermal land for QFN/TDFN EPAD should be connected to GND plane or left floating. For more information refer to http://www.intersil.com/data/tb/TB389.pdf
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Absolute Maximum Ratings
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C Voltage on UP, DN, MUTE or SB with Respect to GND . . . . . . . . . . . . . . . . . . . . .-0.3V to VCC + 0.3 Voltage on AVCC (referenced to GND) . . . . . . . . . . . . . -0.3V to +6V Voltage on VCC (referenced to GND) . . . . . . . . . . . . . . -0.3V to +6V Any Audio Inputs (referenced to VB) . . . . . . . . . . . . . AVCC/2 0.3 Any Outputs (referenced to GND) . . . . . . . . . . .-0.3V to AVCC + 0.3 IOUT max (10s). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30mA Latchup . . . . . . . . . . . . . . . . . . . . . . . . . . Class II, Level A at +85C ESD Rating Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5kV Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .250V
Thermal Information
Thermal Resistance (Typical) JA (C/W) JC (C/W) 20 Lead TSSOP (Note 1) . . . . . . . . . . . 85 N/A 20 Lead QFN (Notes 2, 3) . . . . . . . . . . 40 4 Maximum Junction Temperature (Plastic Package). . . . . . . . +150C Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Temperature Range (Industrial) . . . . . . . . . . . . . . . . . . -40C to 85C Supply Voltage (VCC). . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V Analog Supply Voltage (AVCC). . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V Power Rating of each DCP . . . . . . . . . . . . . . . . . . . . . . . . . . .15mW
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.
NOTES: 1. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 2. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with "direct attach" features. See Tech Brief TB379. 3. For JC, the "case temp" location is the center of the exposed metal pad on the package underside.
Analog Specifications
SYMBOL
Over the recommended operating conditions unless otherwise specified. TEST CONDITIONS MIN (Note 8) TYP (Note 4) MAX (Note 8) UNIT
PARAMETER
DYNAMIC PERFORMANCE (Notes 5, 6) Volume Control Range Mute Mode SNR (Note 7) THD + N (Note 7) XTalk (Note 7) PSRR (Note 7) (Note 7) (Note 7) Signal Noise Ratios (Unweighted) Total Harmonic Distortion + Noise DCP Isolation Power Supply Rejection -3db Cutoff Frequency Noise @1VRMS @1VRMS @ 1kHz, AVCC = 5V @1VRMS @ 1kHz, AVCC = 5V Tap position from 0 to 10 @1kHz, @ tap 10 AVCC = 5V Tap position from 0 to 25 20Hz to 20kHz, VB Input -72 -90 -90 0.01 -100 -90 100 3 0 dB dB dB % dB dB kHz VRMS k +20 +2 -2 -4 0.1 0.5 1 2 0.5 1 2 -20 Tap position 15 10 % % dB dB dB dB dB dB dB dB dB ppm/C
DCP ACCURACY RTOTAL End-to-end Resistance End-to-end Resistance Tolerance DCP Input Resistance Matching Wiper Step Size Tap position from 0 to 26 Tap position from 27 to 31 Wiper Step Size Error Tap position from 0 to 26 Tap position from 27 to 29 Tap position from 30 to 31 DCP-to-DCP Matching Tap position from 0 to 26 Tap position from 27 to 29 Tap position from 30 to 31 Power-up Attenuation (Default Wiper Position at Tap 10) TCV (Note 7) Ratiometric Temperature Coefficient -20 -2 18.5
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Analog Specifications
SYMBOL TCR (Note 7) Over the recommended operating conditions unless otherwise specified. TEST CONDITIONS MIN (Note 8) TYP (Note 4) 340 MAX (Note 8) UNIT ppm/C
PARAMETER Temperature Coefficient of End-to-end Resistance
DC ELECTRICAL SPECIFICATION AVCC VCC tR IAVCC IASB ICC1 ISB VIN VOUT IOUT (Note 5) ROUT VB Analog Power Supply Digital Power Supply AVCC and VCC Ramp Rate Analog Supply Current Analog Standby Current VCC Supply Current VCC Current (Standby) Input Signal on LEFT_IN, RIGHT_IN Pins Output Signal on LEFT_OUT, RIGHT_OUT Pins AVCC = 5.5V, IBIAS = 0mA, IOUT = 0mA for both channels AVCC = 5.5V, IBIAS = 0mA All Inputs = 5.5V, VCC = 5.5V, AVCC = 5.5V VCC = 5.5V Reference to VB pin Reference to GND -AVCC/2 0 -15 2.7 2.7 0.2 5.5 5.5 50 750 360 60 35 AVCC/2 AVCC 15 25 10 AVCC/2 -50 VCC = 5.5V -5 50 5 20 V V V/ms A A A A V V mA pF V mV mA
LEFT_OUT, RIGHT_OUT Buffer Current VCC = 5.5V Buffer Output Impedance
CIN (Note 7) Input Capacitance LEFT_IN, RIGHT_IN Bias Output Voltage VB Accuracy IBIAS VB Output Current VB Output Impedance
Digital Specifications
SYMBOL ILkg VIH VIL
Over the recommended operating conditions unless otherwise specified. PARAMETER TEST CONDITIONS For D0, D1, and D2 MIN (Note 8) -0.3 VCC x 0.7 VCC x 0.1 1.5 2.75 TYP (Note 4) MAX (Note 8) 0.3 UNITS A V V A
Input Leakage Current Input HIGH Voltage Input LOW Voltage
Ics Internal Pull-up Current Source on UP, DN, (Notes 6, 7) MUTE, SB Pins
AC Timing
SYMBOL tPU (Note 7) tWRPO (Note 7)
Over recommended operating conditions PARAMETER Power-up Time to Wiper Stable Wiper Response Time (include tDB and tZAWS ) Auto Increment Starts after UP or DN Input is Keeping Low Auto Increment Rate for the First 4s Auto Increment Rate After 4s MIN (Note 8) TYP (Note 4) 10 35 1 4 8 50 40 1 MAX (Note 8) UNITS ms ms s Hz Hz ms ms s
tDB tLOCK (Note 7) tFLAG_HIGH (Note 7)
Debounce Time Lockout Time after Debounce Time, when any New Command will be Ignored FLAG Delay Time from when Audio Input is Detected to FLAG Asserted HIGH
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ISL22102
AC Timing
SYMBOL tFLAG_LOW tZAWS (Note 7) tLOW tGAP NOTES: 4. Typical values are for AVCC = VCC = 2.7V to 5.0V, TA = +25C. 5. TA = +25C, AVCC = 5.0V; 2Hz to 20kHz Measurement Bandwidth, input signal 1VRMS, 1kHz Sine Wave. 6. When pin is open, voltage is pulled up through current source to VCC. 7. Limits should be considered typical and are not production tested. 8. Parameters with MIN and/or MAX limits are 100% tested at +25C, unless otherwise specified. Temperature limits established by characterization and are not production tested. Over recommended operating conditions (Continued) PARAMETER FLAG Delay Time Interval Step Size, from D2:D0 = 001b to 111b. FLAG is Asserted LOW when Audio Input is Below Threshold. (See Table 1, page 7) Zero Amplitude Detection Time for Wiper Switching Active LOW PU, DN or MUTE Pulse Time Between Two Separate Push-Button Events 20 80 MIN (Note 8) TYP (Note 4) 30 32 MAX (Note 8) UNITS s ms ms ms
Timing Diagrams
tLOW UP (DN, MUTE) tWRPO MI (Note 9) VW tGAP
FIGURE 1. DIGITAL INPUT TIMING
tDB + tZAWS UP
VW 1s
MI (Note 9)
AUTO INCREMENT 4Hz RATE 4s
AUTO INCREMENT 8Hz RATE
FIGURE 2. AUTO INCREMENT TIMING NOTE: 9. MI in these timing diagrams refers to the minimum incremental change of the output (wiper) voltage.
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ISL22102 Pin Descriptions
LEFT_IN, RIGHT_IN
The LEFT_IN and RIGHT_IN pins of the ISL22102 are equivalent to the fixed terminals of a mechanical potentiometer. The stereo audio signal applied to these pins are referenced to VB and may have AVCC/2 maximum amplitude.
SB
The active low SB input allows totally disconnect DCP arrays from their LEFT_IN and RIGHT_IN pins, and move both wipers to position closest to VB pin (as shown in Figure 3). It also sets ISL22102 in low power Standby mode. When SB will be released, the both wipers will be set at position they have prior Standby.
.
LEFT_OUT, RIGHT_OUT
The LEFT_OUT and RIGHT_OUT pins are the buffered wiper terminals of the potentiometers which are equivalent to the movable terminals of a mechanical potentiometers with attached unity gain operational amplifiers (Op Amp). The default output position of wiper terminals preset to -20dB attenuation of input signals.
LEFT_IN (RIGHT_IN)
WIPER_LEFT (WIPER_RIGHT)
VB
VB
This is reference voltage output equal AVCC/2. It is used as common point for audio inputs, as well as reference signal for other system components.
FIGURE 3. DCP CONNECTION IN STANDBY MODE
FLAG
This output pin provides status information to the rest of the system about audio activity. It is High when at least one audio input exceeds VTH threshold, otherwise its output level is Low. The FLAG output can be directly connected to SB pin for automatical setting the ISL22102 in Standby mode.
UP
The debounced active low UP input is increment the wipers position of both channels. An on-chip 2A current source pull-up holds the UP input High. A switch closure to ground or a Low logic level will after a debounce time and Zero Amplitude Crossing Detection, move the wiper to the next adjacent higher tap position. If the UP input signal is held down for 1s, the wipers will auto increment their position with a 4Hz frequency rate for 4s, and then a 8Hz frequency rate (see Figure 2). When the wipers reach their top position of 0dB attenuation, they will stay at this position ignoring any further Up commands.
D0-D2
These three digital input pins allow to program a delay time for FLAG Low output up to 240s. Table 1 lists the D0-D2 settings and corresponding delay times (typical values).
TABLE 1. FLAG PROGRAMMED DELAY SETTINGS D2 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 D0 0 1 0 1 0 1 0 1 DELAY, (s) 0 60 90 120 150 180 210 240
DN
The debounced DN input is decrement the wipers position of both channels. An on-chip 2A current source pull-up holds the DN input High. A switch closure to ground or a Low logic level will, after a debounce time and Zero Amplitude Crossing Detection, move the wiper to the next adjacent lower tap position. If DN input signal is held down for 1s, the wipers will auto decrement their position with a 4Hz frequency rate for 4s, and then a 8Hz frequency rate. When the wipers reach their bottom position of -90dB attenuation, they will stay at this position ignoring any further Down or Mute commands.
CB
This low pass filter terminal requires an external capacitor to GND. The value of this capacitor, together with 5M internal resistor divider, directly determines the PSRR (Power Supply Rejection Ratio) of audio and VB outputs. A 1F to 10F capacitor is recommended.
MUTE
The first active low MUTE input pulse allows both wipers to move, after a debounce time and Zero Amplitude Crossing Detection, to the highest attenuation level of -90dB in one step. The second active low MUTE pulse will return both wipers to their original position, prior to MUTE command. An on-chip 2A current source pull-up holds the MUTE input High.
HPA, HPB
These two high pass filter terminals require an external capacitor of 100nF or higher in-between.
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ISL22102
VTH
This terminal allows to set up the threshold level of audio input to be detected. When audio input to either Left or Right channel is below this threshold - the FLAG output is Low; when audio input is above this threshold - the FLAG output is High. The threshold level is maintained over an external resistor RTH placed between VTH pin, which is a source of 10A current, and VB pin. To calculate the actual threshold we need to multiply 10A by a resistor value and divide the result by 1000. For example, a 100k resistor is a subject of 1mV audio detection threshold, e.g. 10A*100k/1000 = 1mV. Note, the VTH threshold multiplied by 1000 should not exceed 1/2 of AVCC. The maximum resistor value for detection threshold can be found in Table 2.
TABLE 2. RTH vs AVCC AVCC (V) 5.5 5.25 5.0 4.75 4.5 4.25 4.0 3.75 3.5 3.25 3.0 2.75 MAX RTH (k) 188 177 167 156 146 135 125 115 104 94 83 73
internal pull-up so that they normally remain High. When pulled Low by an external push button switch or a logic Low level input, the wipers will be switched to the next adjacent tap position. Internal debounce circuitry prevents inadvertent switching of the wipers position if UP or DN remain Low for less than 15ms, typical. Each of the buttons can be pushed either once for a single increment/decrement or continuously for a multiple increments/decrements. When making a continuous push, after the first second, the device is going to auto increment/decrement mode. If the button is held for longer than 1s, the wiper position will be auto incremented/decremented with a rate of 4Hz for 4s, and with a rate of 8Hz after that. As soon as the button is released, the ISL22102 will return to a low power standby condition. Each wiper acts like its mechanical equivalent and does not move beyond the last position. That is, the counter does not wrap around when clocked to either extreme. Table 3 contains information about attenuation level for each tap position.
TABLE 3. WIPER TAP POSITION vs ATTENUATION TAP POSITION 0 1 2 3 4 5 6 7 ATTENUATION 0 -2dB -4dB -6dB -8dB -10dB -12dB -14dB -16dB -18dB -20dB -22dB -24dB -26dB -28dB -30dB -32dB -34dB -36dB -38dB -40dB -42dB -44dB -46dB -48dB
Device Operation
There are four sections in the ISL22102: the input control, counter and decode section, two resistor arrays with buffered wiper outputs, reference voltage generator of VB output, and audio detection block with programmable delay FLAG output. The input control section operates just like an up/down counter. The output of this counter is decoded to turn on a single electronic switch, connecting a point on the resistor array to the wiper output. Each resistor array is comprised of 31 individual resistors connected in series and its wiper output pass an attenuated audio input to the power amplifier. Both resistor arrays have logarithmic taper with -72dB dynamic range as shown in Table 2. The ISL22102 is designed to interface directly to two push-button switches for effectively moving the wipers up or down. The UP and DN inputs increment or decrement 5-bit counters respectively. The output of these counters are decoded to select one of the thirty-two wiper positions along the resistive array. The wiper increment input, UP, and the wiper decrement input, DN, are both connected to an
8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
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ISL22102
TABLE 3. WIPER TAP POSITION vs ATTENUATION (Continued) TAP POSITION 25 26 27 28 29 30 31 32 ATTENUATION -50dB -52dB -56dB -60dB -64dB -68dB -72dB MUTE (-90dB)
Once an UP, DN or MUTE button has been validly pushed, the left and right inputs are examined for Zero Amplitude Crossing. When either audio input exhibits a zero crossing prior to 32ms, that command is immediately applied to appropriate wiper. If the zero crossing does not occur before the end of 32ms, the command is executed at the end of 32ms period. Zero crossing determines for each channel independently. There is a 40ms lockout time after any of the UP, DN or MUTE button has been validly pushed, when any new command is ignored. If two or more buttons are pressed simultaneously, all commands are ignored upon release of ALL buttons.
Typical Application Diagram
VCC AVCC
VB VB
LEFT_IN RIGHT_IN VB RTH VTH
LEFT_OUT TO POWER AMPLIFIER RIGHT_OUT
FLAG
CB 1F HPA 100nF HPB
SB
VCC*
UP DN MUTE
D2 D1 D0
*FLAG LOW OUTPUT DELAY IS 240s
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ISL22102
Package Outline Drawing
L20.4x4C
20 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 0, 11/06
4X 4.00 A B 6 PIN 1 INDEX AREA 15 1 16 2.0 6 PIN #1 INDEX AREA
16X 0.50 20
4.00
2 .70 0 . 15
11
5
(4X)
0.15 10 6 0.10 M C A B 4 20X 0.25 +0.05 / -0.07
TOP VIEW
20X 0.4 0.10
BOTTOM VIEW
SEE DETAIL "X" 0.10 C C BASE PLANE ( 3. 8 TYP ) ( 2. 70 ) ( 20X 0 . 5 ) SEATING PLANE 0.08 C
0 . 90 0 . 1
SIDE VIEW
( 20X 0 . 25 ) C ( 20X 0 . 6) 0 . 00 MIN. 0 . 05 MAX. 0 . 2 REF 5
TYPICAL RECOMMENDED LAND PATTERN
DETAIL "X"
NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal 0.05 4. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 indentifier may be either a mold or mark feature.
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FN6788.1 January 14, 2010
ISL22102 Thin Shrink Small Outline Plastic Packages (TSSOP)
N INDEX AREA E E1 -B1 2 3 0.05(0.002) -AD -CSEATING PLANE A 0.25 0.010 L 0.25(0.010) M GAUGE PLANE BM
M20.173
20 LEAD THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A A1 A2 b c MIN 0.002 0.031 0.0075 0.0035 0.252 0.169 0.246 0.0177 20 0o 8o 0o MAX 0.047 0.006 0.051 0.0118 0.0079 0.260 0.177 0.256 0.0295 MILLIMETERS MIN 0.05 0.80 0.19 0.09 6.40 4.30 6.25 0.45 20 8o MAX 1.20 0.15 1.05 0.30 0.20 6.60 4.50 6.50 0.75 NOTES 9 3 4 6 7 Rev. 1 6/98
e
b 0.10(0.004) M C AM BS
A1 0.10(0.004)
D
A2 c
E1 e E L N
0.026 BSC
0.65 BSC
NOTES: 1. These package dimensions are within allowable dimensions of JEDEC MO-153-AC, Issue E. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E1" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension "b" does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of "b" dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. (Angles in degrees)
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 11
FN6788.1 January 14, 2010

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